Direct mapping
Recover coordinates from each output index; support general convolution geometry.
GROUPCONV ATLAS · RTX 4090 · FP32
Grouped convolution, measured across the whole map.
Four CUDA implementations, eighty shapes, two timing boundaries. k3 computes four adjacent outputs per thread and improves on the direct kernel. Against tuned PyTorch, the advantage survives only in part of the map.
A substantial improvement over k0.
The 80-shape geometric mean favors the library.
Graph device timing · geometric mean of 80 shapes. Baseline latency ÷ k3 latency; above 1× favors k3.
SHAPE · BASELINE · TIMING BOUNDARY
Start with k3 against tuned PyTorch. Switch from graph-device timing to the synchronized API, then select a shape to compare both readings side by side.
CUDA · MAPPING · DATA REUSE
These are four implementations with different work assignments. Shared memory adds cooperation and synchronization; keeping four neighboring outputs in one thread makes a different tradeoff.
Recover coordinates from each output index; support general convolution geometry.
Specialize the geometry and map threads to output space, reducing general indexing work.
Load the input tile and its halo together, then read shared memory. Supports 1, 2 or 4 channels per group.
Compute four adjacent horizontal outputs in one thread and reuse overlapping input windows.
Diagrams illustrate work assignment and reuse, not thread counts or hardware layout. Counts show support within the 80-shape Atlas.
Across six supported Nsight examples, k2 is shorter than k1 at two points and longer at four. The shared halo is useful work with a cost, not a guaranteed speedup.
Single profiling captures help inspect the mechanism; the Atlas uses ordinary timed batches for its confidence classifications.
Read the counters and machine-code evidenceMOBILENETV2 · FEATURES[3] · ONE CONVOLUTION
A useful kernel must survive the surrounding work. In a MobileNetV2 block, one convolution is replaced by k3 while the rest of the block stays in place.
MobileNetV2 · features[3]original block / one k3 substitution
Graph device
1.14×WINDevice events inside CUDA Graph
1.13849×
Synchronized API
0.68×LOSSThe call, including synchronization
0.67902×
The graph keeps a 1.14× gain. The synchronized call falls to 0.68×.
Ratios compare the entire block, with random weights and one replaced convolution. Ten paired batches; 95% bootstrap intervals; 5% practical threshold. Model accuracy and whole-network speed were not evaluated.
Inspect the module resultSOURCE · METHOD · RECORDS
Every cell keeps its shape, comparison, interval and status. The public repository contains the kernels, analysis and reproduction commands; the site reads the same audited records.
FP32 · contiguous NCHW · 3×3 · stride and dilation 1 · padding 1 · no bias.
Full-output numerical checks and independent FP64 points; unsupported cases remain in the record.
Ten paired batches, 95% bootstrap intervals and a 5% practical threshold describe this session.
/case-studies/groupconv-atlas/rtx4090-atlas.jsonCommit-local file · unpublishedSHA-256: 098a722a9cc72563f75d6a285e4953b6c57e972432b9a86ef4873585c7da79cd/case-studies/groupconv-atlas/rtx4090-shapes.jsonCommit-local file · unpublishedSHA-256: 904644af9daa5ea9bb5e9c32a53b24f1981618f9bc8baf14957d17f684a0ba18/case-studies/groupconv-atlas/map-details.jsonCommit-local file · unpublishedSHA-256: b3e2358b855add84420521efde20e2ec7402ae60b6b8b4cea2466fa8d49863a4/case-studies/groupconv-atlas/atlas.jsonCommit-local file · unpublishedSHA-256: ba505546a2568d8251a19b7f549fe66197f8ccc9428ea126f74b7c8a60a33d27/case-studies/groupconv-atlas/current-evidence.mdCommit-local file · unpublishedSHA-256: c13925190954b6be27139f3fb83f36983114c195e06dd0022e07a200d8f8d961/case-studies/groupconv-atlas/provenance.jsonCommit-local file · unpublishedSHA-256: 317e77a65c3154902ca72e725c9517ee8793c326c7ba1f7da2403cbf94de6742RTX 4090 · 8 September 2026. Historical RTX 4090 D and Apple OpenCL runs are separate. Code: MIT; data and figures: CC BY 4.0, Xiangguo Zhang.
Designed and implemented the grouped-convolution kernels, built the numerical validation and benchmark pipeline, and analyzed performance across shapes and timing boundaries.
Record NCHW geometry, groups and support limits before measurement.
Compare complete FP32 outputs; keep independent FP64 checks separate.
Graph-internal CUDA events and synchronized eager API measure different boundaries.
Inspect shape-level results, including regressions and unsupported cases.
The Atlas keeps every supported and unsupported result visible. Ratios above one favor the candidate; ten paired batches support within-session bootstrap classification.
No overall advantage over tuned PyTorch; graph timing is not eager kernel timing.
A fixed MobileNetV2 block substitution won graph timing at N=4 (1.13849×), but lost synchronized eager API at N=1 and N=4. Random weights; no model accuracy evaluation.
Frontend, Triton and Nsight evidence was audited separately on RTX 4090. Historical RTX 4090 D and Apple OpenCL remain separate; sustainable roofline bounds are not established.